1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a novel packaging process by depositing solder balls or columns on the substrate at the chip joining sites. A major purpose of the invention is to reduce the wafer level processes thus reducing the total processing cost of the flip chip package, shortening the cycle time for flip chip implementation and improving the reliability and performance of the flip chip packages.
2. Description of the Prior Art
General practice for bonding a flip chip to a substrate with existing bonded die design or layout is limited by several technical difficulties and cost considerations. Specifically, under certain applications, the bonding pitch for the flip chip is not able to satisfy the higher I/O (input/output) density requirement when the bonding pitch is less than 8 mils. This technical difficulty arises from current state of art wafer-level shadow mask evaporation or screen printing process. Current techniques for wafer-level bumping are generally limited to processes for depositing the solder balls by evaporation through a shadow mask, or solder paste on a wafer or die by using paste screen and reflow technique to generate solder bumps on the wafer. Furthermore, due to the processing steps required for xe2x80x9cbumpingxe2x80x9d the wafer or die, the production costs of the flip chip packages are considerable higher than that of the wire-bonding or the tap automatic bonding (TAB). For these reasons, even that flip-chip in a package (FCIP) offers the advantages of small footprint, low profile, improved electrical performance, and efficient die-back heat-removal, application of flip-chip for electronic packaging is still limited to a very small percentage of high-performance and high-cost devices.
In addition to the difficulties in achieving a fine resolution for solder paste screen in xe2x80x9cbumpingxe2x80x9d the wafer, considerations must also be given to the problems arising from difference in thermal expansion coefficient between the substrate and electronic device mounted thereon. In order to compensate for the differences in thermal expansion, the volume of solder paste bumped onto the flip chip must be carefully controlled to provide sufficient standoff height of the flip chip above the substrate. Integrity and reliability of the solder joints between the flip chip and the substrate thus depends on the standoff heights of the solder paste bumps placed onto the wafer. Special care and heavy emphasis in technology developments are concentrated on how to deposit and control the solder paste volume in order to achieve well-controlled standoff heights. However, this additional precision requirement in bumping the chip further increases the production cost of the flip chip packaging.
Modern semiconductor packages implementing flip chip typically includes a process to attach a flip chip to a printed wiring board (PWB) such as a FR-4 epoxy fiber glass board. The wafer is first bumped with lead/tin solder pads, which constitute the signal input/output (I/O), power and ground terminals on the integrated circuits (IC) fabricated on the wafer. Lead-tin solder with low-melting temperature is also applied to the pads of the board usually in the form of solder paste. The substrate has a matching footprint of these solder wettable pads. The bumped wafer is then flipped and placed in an aligned manner to the substrate to align the solder pads on the substrate and the bumps on the wafer. The IC chip is then joined to the substrate with a reflow process. As described above, the technique is limited by the resolution achievable through a paste screen process. Further reduction of pitch below 8 mils is generally difficult to accomplish by employing this technology. Due to requirement perform the bumping process in the wafer level, production costs are generally quite high for the reasons to be further discussed when compared to the techniques disclosed in this invention.
In U. S. Pat. 5,564,617 entitled xe2x80x9cMethod and Apparatus for Assembling Multi-chip Modulesxe2x80x9d (issued Oct. 15, 1996), Degani et al. disclose a multiple chip module which is assembled using a flip-chip bonding technology. Stencil printable solder-paste and surface mount equipment for interconnecting signaling input/output contact pads on devices within such a multiple-chip module. The flip chip bonding technique is simplified by use of a solder paste. The solder paste has the desirable characteristics of reflow alignment, fluxing and printability thus allowing the application of standard surface mount equipment High volume production of standard inexpensive modules is achievable to provide high-density interconnections. However, Degani""s patented method is limited by the technical difficulties that the resolution is limited both by the precision in controlling the solder paste and the screen technique.
Degani""s patented method is further limited by the problems arising from difference in thermal expansion coefficient between the substrate and the mounted electronic device. Again, in order to compensate for the differences in thermal expansion, the volume of solder paste bumped onto the substrate must be carefully controlled to provide sufficient standoff height of the flip chip above the substrate. Integrity and reliability of the solder joints between the flip chip and the substrate thus depends on the standoff heights of the solder paste screen-printed onto the substrate. Special care and emphasis in technology must be developed on how to deposit and control the solder paste volume in order to achieve well-controlled standoff heights. Therefore, this additional precision requirement in controlling volume of the solder-paste printed onto the substrate further increases the production cost in applying Degani""s technology to flip chip packaging.
Therefore, a need still exits in the art to provide an improved structure and procedure for implementing the flip chip in electronic packages such that the difficulties and limitations described above can be overcome. It is further desirable that the improved procedure provides packaging configurations and process to conveniently control the standoff height of the flip chip and to reduce the surface tension at the soldered joints such that more reliable high performance electronic packages can be provided at a lower cost
It is therefore an object of the present invention to provide a new flip chip packaging method implemented with new structural and metallurgical features in order to overcome the aforementioned difficulties encountered in the prior art.
Specifically, it is an object of the present invention to provide a new flip-chip packaging process wherein a pre-designated number of solder balls are placed on a substrate corresponding to input/output signal terminals of the flip chip to simplify the packaging process. More costly and complicated bumping processes of solder evaporation or solder photolithographic plating performed on the wafer are no longer required.
Another object of the present invention is to provide a new flip-chip packaging process wherein a pre-designated number of solder balls are placed on a substrate. The placement of the solder balls corresponds to the locations of the input/output signal terminals of the flip chip. Higher precision of connection placement is provided such that a lower pitch can be achieved. Smaller pitch of connections can be accomplished without being hindered by the resolution limitation when a paste screen technology is applied on either the wafer or the substrate
Another object of the present invention is to provide a new flip-chip packaging process wherein a pre-designated number of solder balls are placed on a substrate. The solder balls are placed corresponding to input/output signal terminals of the flip chip. Also, specially configured solder balls are employed to produce a required standoff height. The difficulties of precisely controlling the amount of solder pastes for bumping the wafer or for depositing on the substrate are thus eliminated and the packaging process is greatly simplified.
Another object of the present invention is to provide a new flip-chip packaging process wherein a pre-designated number of either solder balls with core or column are placed on a substrate. The solder balls are placed corresponding to input/output signal terminals of the flip chip. The column type of joints can be conveniently formed to further reduce the pitch between the joints while minimize the costly wafer level processes.
Another object of the present invention is to provide a new flip-chip packaging process wherein a pre-designated number of either solder balls with core or column are placed on a substrate. The spaces between the solder balls are then filled with specially processed stratified under-filling materials. The stratified under-filling materials produce a stress-gradient during the thermal expansions experienced in the temperature cycles during the manufacturing processes. The package integrity is improved by greatly reducing the likelihood of de-lamination while prolonging the fatigue life of solder joints.
Briefly, in a preferred embodiment, the present invention includes an improved method for carry out a flip chip packaging process for attaching a semiconductor integrated circuit (IC) wafer having a plurality of input/output terminals, to a substrate. The method includes the steps of 1) securely placing a plurality of solder balls on the substrate with each of said solder balls corresponding to a location of one of the input/output terminals on the integrated circuit wafer; 2) flipping the integrated circuit wafer for aligning each of the input/output terminals of the IC wafer to one of the solder balls; and 3) mounting the IC wafer onto the substrate for placing the I/O terminals on a corresponding solder ball and applying a reflow temperature for soldering the IC wafer to the substrate.